Z-zero launches Z-planner and Z-solver for PCB Stackup Design
Redmond, Washington, November 1, 2017– Z-zero announced today the launch of two new software products —Z-planner, for PCB stackup design and materials selection; and Z-solver, for quick, accurate impedance and insertion loss results.
Z-planner is a field-solver based PCB stackup planning and materials selection tool that’s optimized for hardware engineering teams that may or may not be familiar with the exhaustive details of the laminate and PCB-fabrication processes.
Lee Ritchey, author of “Right the First Time” and founder of high-speed design-consulting firm Speeding Edge, said, “Far too many engineering teams leave stackup design, which is critical to signal integrity, to PCB fabricators, who are—more often than not—working with little electrical engineering expertise.” Lee went on to say, “As someone who’s designed more than 1,000 stackups over the years, I must say that I find Z-planner to be an exceptional stackup-planning tool. It has the most comprehensive library of laminates I have seen, and is very user friendly. It would be an excellent addition to any signal integrity engineer’s tool set.”
Version 2017.1 includes an import/export interface with Mentor Graphic’s HyperLynx signal-integrity software. HyperLynx users can bring legacy stackups into Z-planner, and take advantage of some of the additional features and functionality in Z-planner, including the materials library and awareness of glass styles, resin contents, pressed prepreg thicknesses, the frequency-dependence of dielectric constants (Dk) and dissipation factors (Df), and automation of the PCB stackup design process. Engineering teams that care enough about signal integrity, crosstalk, and EMC effects to have purchased signal-integrity simulation software should find Z-planner to be an accuracy-increasing addition to their high-speed design flow.
Since most hardware designers are comfortable representing PCB stackups using spreadsheets, Z-planner is architected to look and operate like one. The tool bridges the sizable gap between the spreadsheets many engineers and fabricators use to describe their stackups and the PCB signal-integrity world. High-speed analysis is often done with inadequate materials details, including key parameters that laminate manufacturers and PCB fabricators consider as laminates are produced and pressed into circuit boards.
Z-planner v2017.1 also includes a bidirectional IPC-2581 interface, a format supported by many fabricators and electronic-design software tools, and additional interfaces are in work for future versions.
Using spreadsheets, engineers often take Dk and Df values from laminate manufacturers’ datasheets for simulations, ignoring resin content and frequency, or relying heavily on third-party fabricators to resolve final-implementation details with stackup and materials selection long after signal-integrity simulations have been performed — sometimes inaccurately — on a design.
Prior to the release of Z-planner, no software on the market accessibly considered the major issues —known primarily only by fabricators — surrounding stackup design, and combined them with an accurate field solver and loss-planning environment, a complete dielectric materials selection library, and seamless interfaces to popular PCB signal-integrity software — all bundled into a powerful, affordably priced, easy-to-use tool.
How can Z-planner assist your PCB stackup design?
Z-zero’s Z-solver provides the most reasonably priced path to making what-if tradeoffs between Dk, Df, physical trace topologies, and spacing — with results that include single-ended impedance, differential impedance, propagation delay, loss as a function of frequency, and the effects of copper roughness.
About Z-zero
Z-zero, based in Seattle, Washington, develops PCB stackup planning and material-selection software for electronic-system design. For further information or to download a free evaluation of the software and stackup-design tutorial, please visit z-zero.com.